This invention is in the field of integrated circuits, such as those including solid-state memory. Embodiments of this invention are more specifically directed to static random access memory (SRAM) cells and devices.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems. Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM but also in SRAM realized as “stand-alone” memory integrated circuit devices. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written, or retain a stored data state, as expected.
FIG. 1a illustrates an example of conventional SRAM cell, which is constructed in the well-known six-transistor (6-T) arrangement. In this example, cell 2 is in the jth row and kth column of a memory array of similar cells. SRAM memory cell 2 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 2 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor 3a and n-channel driver transistor 4a, and the other inverter of series-connected p-channel load transistor 3b and n-channel transistor 4b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 3a, 4a constitutes storage node SNT, and the common drain node of transistors 3b, 4b constitutes storage node SNB, in this example. N-channel pass transistor 5a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass transistor 5b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass transistors 5a, 5b are driven by word line WLj for this jth row in which cell 2 resides.
In its normal operation, bit lines BLTk, BLBk are typically precharged by precharge circuitry 7 to a high voltage Vddp (which is at or near power supply voltage Vdda) and are equalized to that voltage; precharge circuitry 7 then releases bit lines BLTk, BLBk to then float during the remainder of the access cycle. To access cell 2 for a read operation, word line WLj is then energized, turning on pass transistors 5a, 5b, and connecting storage nodes SNT, SNB to bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 2 to latch in the desired state.
One type of failure mechanism observed for SRAM cells such as cell 2 is a cell stability failure, also referred to as a “disturb” failure or as insufficient static noise margin, in which noise of sufficient magnitude coupling to the bit lines of unselected cells, for example during a write to a selected memory cell in the same row, can cause a false write of data to unselected cells in that same row. In effect, such noise can be of sufficient magnitude as to trip the inverters of one or more of the unselected cells (i.e., the “half-selected” cells in unselected columns of the selected row). Cell stability failures can occur in cases in which the drive of the SRAM cell driver or load transistors is mismatched relative to other transistors in the cell. For example, if cell 2 of FIG. 1a is storing a “0” data state (storage node SNT at a low level), weakness of one or both of the “on” state driver transistor 4a and load transistor 3b relative to the “off” state driver transistor 4b and load transistor 3a causes the latch of cell 2 to more easily change state when pass transistors 5a, 5b are is turned on during an access to its row j. More specifically, the “trip” voltage of cell 2 for the “0” to “1” transition will be higher than desired due to this relative weakness of transistors 3b, 4a, causing the state of cell 2 to “flip” in response to a smaller voltage drop at storage node SNT than would be required for the balanced cell. In other words, the stability of cell 2 to noise, such as that encountered when “half-selected”, is reduced by this transistor imbalance.
Another failure mechanism of SRAM cells is a write failure, which occurs when an addressed SRAM cell does not change its stored state in response to a write of the opposite data state from that stored. Write failures are the converse of cell stability failures—while a cell stability failure occurs if a cell changes its state too easily, a write failure occurs if a cell is too stubborn in changing its state, specifically by the write circuitry being unable to pull down the storage node that is currently latched to a high voltage.
For example, if cell 2 of FIG. 1a is initially storing a “0” data state (storage node SNB at a high level, with load transistor 3b on and driver transistor 4b off), the opposite “1” data state will be written by a low level driven at bit line BLBk by write circuitry, and coupled to storage node SNB via the “on” state pass transistor 5b. Weakness of pass transistor 5b reduces the ability of the low-side bit line BLBk to overcome the opposing drive of load transistor 3b, leading to failure of this write cycle to change the cell state. Weakness of driver transistor 4b reduces the feedback effect from storage node SNT being pulled high by load transistor 3a (as driver transistor 4b begins to turn on due to the low level at bit line BLBk) in this write operation, further reducing the writeability of cell 2. Weakness of load transistor 3a will also be reflected in weaker pulling high of storage node SNT, further reducing the feedback effect in this write cycle. The likelihood of write failure is thus increased by such device imbalance.
Accordingly, as well known in the art, balance in the electrical characteristics of load transistors 3a, 3b in the same SRAM cell relative to one another, and between driver transistors 4a, 4b in the same cell relative to one another, is conducive to both cell stability and writeability. As such, conventional SRAM cells are typically formed so that load transistors 3a, 3b match one another in construction as closely as possible, so that driver transistors 4a, 4b match one another in construction as closely as possible, and so that pass transistors 5a, 5b match one another in construction as closely as possible. This close matching of construction (i.e., matching in layout and also in dopant profiles and film thicknesses) between these paired transistors is designed to result in closely matched electrical characteristics of those paired devices.
Electrical effects dependent on the proximity and structure of neighboring devices have been observed in transistors constructed with deep sub-micron feature sizes (e.g., gate widths of 90 nm and below). Various causes and manifestations of these “proximity” effects have been characterized. These various proximity effects have been observed to impart significant variations in drain-to-source current of MOS transistors.
One known type of proximity effect involves the extent to which the photolithographic patterning of a polysilicon gate structure is affected by other nearby gate structures. Regularity in gate spacing and width is known to reduce variation due to these lithographic proximity effects. Lithographic proximity effects have also been observed at the contact level. In addition, nearby contact openings in overlying insulator films have been observed to affect strain effects in MOS transistors, depending on the stresses (i.e., compressive or tensile properties) in that overlying film.
As described in Drennan et al., “Implications of Proximity Effects for Analog Design”, Paper 8.6, Custom Integrated Circuits Conference (IEEE, 2006), another source of strain-related proximity effects on MOS transistors is referred to as the Shallow Trench Isolation stress effect. Strain variation due to this effect results from stresses within the shallow trench isolation structures that define active regions (e.g., source and drain regions) of MOS transistors. As known in the art, relatively thick isolation dielectric (e.g., silicon dioxide) structures at selected surface locations of the integrated circuit define semiconductor active regions into which MOS transistors and other semiconductor circuit elements are formed. In modern integrated circuits, particularly those in the sub-micron regime, this isolation dielectric is formed by a masked recess etch into the surface of the substrate (or silicon layer in a silicon-on-insulator environment), followed by deposition of a dielectric film such as silicon dioxide into those recesses. The deposited silicon dioxide in these “shallow trench isolation” structures can exhibit compressive or tensile properties, which can impart strain to the neighboring active regions including MOS transistor channel regions. The extent of this imparted strain has been observed to depend on the proximity of the transistor to the shallow trench isolation structure, as well as the volume of the isolation dielectric itself (i.e., the proximity and size of a neighboring active region on the other side of the isolation structure).
By way of further background, recent advances in semiconductor technology as applied to integrated circuits include the use of “strain engineering” (or, alternatively, “stress engineering”) in the manufacture of semiconductor device structures. This technology “tunes” strain in the crystal lattice of MOS transistor channel regions to enhance carrier mobility in those regions, which increases the source/drain current (i.e., drive strength) of the transistor in both the triode and saturation regions. In a general sense, compressive stress enhances hole mobility in the channel region of a p-channel MOS transistor, and tensile stress enhances electron mobility in the channel region of an n-channel MOS transistor. Known approaches in accomplishing this tuning include the use of “embedded SiGe” (or “eSiGe”), in which the source and drain regions of a p-channel MOS transistor structure are etched from the silicon substrate or well region, and are replaced with a silicon-germanium alloy formed by selective epitaxy. The germanium atoms within the silicon crystal lattice cause the eSiGe alloy to exhibit a larger lattice constant, thus applying compressive stress to the channel region of the p-channel MOS transistor. Another conventional strain engineering approach known as “dual stress liner”, or “DSL”, technology involves the formation of a silicon nitride layer of tensile or compressive characteristics over the active regions (i.e., source and drain regions) of n-channel and p-channel MOS transistors, respectively. However, it has been observed that the effects of these strain engineering techniques often extend to neighboring devices and structures, amounting to another type of “proximity effect”.
Another proximity effect that has been observed in sub-micron integrated circuits is the cross-diffusion of implanted dopant species. If source/drain regions of neighboring or nearby transistors are formed by ion implantation at different doses, the resulting dopant concentration gradient may be sufficient to cause dopant ions to diffuse from a more heavily-doped source/drain region to a nearby more lightly-doped source/drain region. This of course can cause deviation from design for either or both of the affected transistors.
As known in the art, memory arrays involve a relatively large area of similar structures (i.e., the memory cells), and as such are conducive to being constructed in very regular fashion. This regularity in construction will, theoretically, reduce variation in array transistor performance due to proximity effects. This constraint can be enforced well in memory arrays in which all of the transistors are of substantially the same size, such as arrays of 6-T SRAM cells such as described above relative to FIG. 1a. Memory cells at the edges of the array can be protected from proximity effects and cross-diffusion by the construction of “dummy” memory cells around the edges of the memory array. These dummy cells are constructed similarly as the memory cells themselves, but without electrical connection.
Other types of integrated circuit functions that are also constructed as an array or region of repetitive device structures, similarly suffer from device variations due to proximity effect. For example, many modern logic circuits are constructed as a “sea of gates” or another type of repetitive construction at lower levels in the integrated circuit structure. These logic circuits can be readily customized to realize a particular logic function at upper structural levels, such as in the routing of metal conductors to the transistors and gates. Proximity effects similarly result in transistor performance variation between transistors and gates at the edges of the repetitive structures, and those in the interior of the logic array.
By way of further background, SRAM cells of the cross-coupled inverter latch type that have an additional read buffer are known in the art. FIG. 1b illustrates an example of such an SRAM cell 2′, which adds a two-transistor buffer to the 6-T construction described above in connection with FIG. 1a. In this example, “8-T” SRAM cell 2′ includes a single-sided read buffer constructed of n-channel MOS transistors 6, 8 with their source/drain paths connected in series between read bit line RD_BLk for column k in which cell 2′ resides, and a ground voltage Vssb (which may be at the same or a different voltage from array ground voltage Vssa). The gate of transistor 6 is connected to storage node SNB, while the gate of transistor 8 is connected to read word line RD_WLj, which is the word line asserted in read cycles for row j in which cell 2′ resides. Conversely, the gates of pass transistors 5a, 5b of cell 2′ are connected to write word line WR_WLj, and the source/drain paths of pass transistors 5a, 5b are connected between their respective storage nodes SNT, SNB, and write bit lines WR_BLTk, WR_BLBk, respectively. As such, the state of cell 2′ appears at read bit line RD_BLk in a read cycle selecting cell 2′, and is written from write bit lines WR_BLTk, WR_BLBk in a write cycle selecting cell 2′.
Typically, 8-T SRAM cells such as cell 2′ of FIG. 1b are implemented in those situations in which additional read current is to be sourced from the cell, beyond that which may be available from latch driver transistors 4a, 4b. More specifically, the 8-T cell is attractive in those designs in which cell transistors 3, 4 are to be fabricated as minimum feature size devices to attain high density and easy writeability, but in which the read current from those small devices is sub-optimal for the sense circuitry. As such, buffer transistors 6, 8 are generally constructed to be much larger (i.e., with relatively large channel widths) than latch transistors 3, 4, and pass transistors 5. In order for each cell 2′ to be constructed with its own read buffer, these larger transistors must necessarily be placed within the same “bit cell” layout in the array, thus interspersing the larger buffer devices among the smaller (e.g., minimum feature size) latch and pass transistors of the cells.
However, as discussed above, the incorporation of larger buffer transistors adjacent or nearby to the smaller transistor can give rise to proximity effects and cross-diffusion effects. As a result, conventional 8-T SRAM cells 2′ are able to provide improved read current, but at a price of potential imbalance in the operation of the latch portion of the cells 2′. These effects are particularly noticeable with memories constructed with the deep sub-micron transistor sizes now common in modern integrated circuits.
By way of further background, 6-T cells with asymmetrically constructed pass transistors are known in the art. In these conventional asymmetric cells, referring to FIG. 1a, pass transistors 5a, 5b have source regions (i.e., at the side connecting to bit lines BLTk, BLBk, respectively) that are constructed differently from their drain regions (i.e., at the side connecting to storage nodes SNT, SNB). The asymmetry is implemented so that the source/drain current is stronger for write operations (i.e., for discharging one of storage nodes SNT, SNB to the corresponding low level bit lines BLTk, BLBk) than for read operations (i.e., for pulling one of precharged bit lines BLTk, BLBk to the lower level storage node SNT, SNB). This pass gate asymmetry can be accomplished by asymmetric source-side “halo” implantation at a large angle from the normal, for example with the gate electrode shadowing the implant on the drain side, in the formation of the source/drain regions of pass transistors 5a, 5b. 
By way of further background, the construction of unmatched pass transistors in 6-T SRAM cells is also known in the art. According to this conventional approach, one bit line serves as a “read bit line” and the other serves as a “write bit line”. The pass transistor coupled to the “read bit line” is constructed to have stronger drive than the pass transistor coupled to the “write bit line”, for example by having a larger channel width, to provide a strong read current and thus a short access time. The weaker pass transistor for the “write bit line” can be of minimum feature size (i.e., smaller channel width) since the write mechanism can extend over the full cycle and is thus not as timing-critical as the read access time.